1. Field of the Invention
This invention relates to phase-locked loops, and more particularly to phase-locked loops with selectable input clock signals.
2. Description of the Related Art
In optical communication systems, line cards compliant with standards such as Synchronous Optical Network (SONET) or Synchronous Digital Hierarchy (SDH) (the European counterpart to SONET) utilize clock generation circuits to generate clocks used in data transmission and reception. In such clock generation circuits, a phase-locked loop (PLL) receives an input reference clock and generates one or more high-speed clocks suitable for use in transmitting or receiving data in a SONET or SDH based system. According to one aspect of those communication systems, multiple reference clocks may be supplied to a clock generation circuit to provide a variety of capabilities, including redundancy. When the PLL in the clock generation circuit switches from using one input reference clock to using another input reference clock, a phase glitch may arise due to an arbitrary phase relationship between the two input clocks. Such phase changes in the output clock can introduce transmission errors or other problems.
In order to reduce or eliminate phase glitches when switching between input clocks, one approach to achieve such “hitless switching” is to set the bandwidth of the PLL used to multiply the reference clock to be very low, e.g., on the order of Hz. With the low-bandwidth PLL, even if the phase difference between the input clocks is relatively large, the output phase change resulting from switching input reference clocks used by the PLL would occur relatively slowly. The low-bandwidth PLL implementation can meet the tight phase transient requirements and thereby reduce or eliminate transmission errors associated with switching reference clocks. However, low-bandwidth PLLs suitable for meeting tight phase transient requirements may be difficult to implement in a monolithic integrated circuit and may be expensive or difficult to implement with discrete components. In addition, low-bandwidth PLLs typically achieve lock relatively slowly and typically generate output clocks having increased jitter due to reduced filtering of the output of a voltage-controlled oscillator (VCO) included in the PLL. In some applications, a maximum time interval error (MTIE) is specified (e.g., an MTIE of 1000 ns), which is a limit on the amount of phase movement as a function of time after a switch between input clocks, and generally cannot be satisfied merely by adjusting the PLL bandwidth.